Modular J-PET delivers data

Sometimes in research it takes a lot of effort, time and patience to get something running. But then when it runs – the satisfaction is granted.

It has been exactly 5 years since the Data Acquisition System  for the first J-PET prototype said *beep* and provided first tomography data from the scanner constructed out of plastic scintillators.

During these 5 years, we designed, constructed and eventually successfully launched  a completely new vision of PET tomography – a lightweight, modular scanner with a compact and powerful data processing system.

24 modules have 13 plastic scintillator strips and 54 SiPMs on each end. The signals they generate are registered by Artix7 based front end boards that digitize the signals and send the data to 4 data concentrators which are Virtex Ultrascale VCU108 boards from Xilinx. The entire system is controlled by a single Zynq Ultrascale+ ZCU102 board – all interconnected and synchronized by a ton of optical links.

The concentrator boards preprocess the raw data extracting time coincidences, applying calibrations and converting it into reconstructed interaction points on the modules. Such data stream is sent to the storage using UDP and 10GbE links but additionally transferred to the controller board for to be developed real-time image reconstruction. At this moment we have the software visualization using J-PET Software Framework which delivers first insight into the data – a radioactive source placed in the center of the barrel.

It’s something! Now we design a system for a Total-Body Tomography – a scanner capable of monitoring radiopharmaceutical marker distribution over the entire human body in a single shot.

[image K.Kacprzak]


Congratulations to Mateusz Guzik for receiving a prize for the best master thesis at the Faculty of Mechanical Engineering and Robotics AGH University of Science and Technology in Cracow!

Mateusz investigated scrubbing and logic redundancy methods to mitigate radiation induced errors on an image processing pipeline project. Everything on a small #zybo board. This topic was especially important to Mateusz as he is a member of AGH Space Systems #aghspace – a very strong group developing space-related technologies.

You can find the awarded thesis in the Results section

ALveo u280 from XUP

We have just received two Xilinx Alveo U280 as a donation from the Xilinx University Program.

Many thanks to Xilinx for this generous donation!

These two cards, together with the Alveo U50 we bought earlier will be the foundation for the FPGA accelerated computing infrastructure we are designing within the Hardware Acceleration Lab.

Two most-advanced accelerator cards will allow to experiment with our Lattice QCD kernels in a multi-node environment, where the networking and efficient kernel-to-kernel communication over PCIe bus and QSFP+ will be key elements.

First alveo up and running

Couple of weeks ago we have acquired our first Xilinx Alveo U50.

Turns out that setting it up and running first bitfiles easy, especially using Alveo-Pynq and Jupyter notebooks!

It’s only about 15 lines of code to access your accelerator card, configure with a bitfile, allocate memory, transfer data and run the kernel.

Below you can find all links required to configure and operate Alveo cards:

  • Xilinx Runtime and Deployment Target Platform: [link]
  • Alveo-PYNQ: [link]

Hardware Acceleration Lab

FPGAFAIS has become a part of the Hardware Acceleration Lab – a new, cross-department entity at Jagiellonian University, originating from the Strategic Program Excellence Cluster and DigiWorld – one of the priority research area.

Hardware Acceleration Lab gathers experts from various fields connected by computing acceleration such as: GPGPU, FPGA, networking, system design, algorithm optimization.

4 research groups have been formed within the Lab:

Computing Systems: design and development of high performance computing platforms for: general HPC, online data processing infrastructure for large scale physics experiments and 5G

Hardware Acceleration on FPGAs: application of FPGAs for various computing problems for both Edge and Cloud

Programming of novel computer architectures: development and optimization of programming frameworks used for main computing problems, such as AI and simulations

Internet-Of-Things / Edge-Computing: technology and algorythmics for autonomous vehicles, sensors fusion and Edge-AI

one of the first to get hololens2

Today we have received Microsoft Hololens 2 as the first batch of this sweet hardware has been shipped worldwide.


FPGAFAIS and Jagiellonian University are one of the first to have this equipment available for research.

The holographic goggles are intended to be used for J-PET project and visualization of tomographic measurement in real-time on the patient but it offers so much possibilities.

The goggles run Windows 10 and can be programmed in C# using Unity game engine and Vuforia. In case you have some experience in these technologies, don’t hesitate to join our group.

If you are interested, have an idea for an interesting project, have a look at diploma projects tab or email directly at

Many thanks to Bechtle AG for assisting us with the purchase.

Accelerating HPC

It took some time, a lot of research and development to make this very important step!

Trying to employ latest technologies, we have implemented, compiled and successfully run the accelerated Conjugate Gradient solver on Alveo U280 (shell 2019.2) using Vitis, both officially released just couple days ago.

In this design we are evaluating some of techniques like:

  • Integrated HBM memory
  • Fully streamlined kernel

We have managed to fit 3 instances of the kernel into the device, consuming about 70% of available resources.

Each kernel instance works with Iteration Interval of 2 clock cycles at 300 MHz, that gives almost 600 GFLOPs for the entire solution!

ACAP architecture for neural networks

ACAP (Adaptive Compute Acceleration Platform) devices are complex System-on-Chips including programmable logic resources, ARM cores, DSP and AI engines. All these, combined together can offer new capabilities in netural networks inference. Such complex systems require advanced development environments in order to make use of all possible features.

The aim of this project is to investigate capabilities of ACAP devices and software packages for neural networks inference


  • Basic knowledge of neural networks
  • Basic knowledge of C/C++ programming
  • Basic knowledge of FPGA technology

Układy typu ACAP (Adative Compute Acceleration Platform) są złożonymi systemami SoC zawierającymi zasoby programowalnej logiki, rdzenie ARM oraz silniki DSP i AI. Wszystkie połączone razem otwierają nowe możliwości do inferencji sieci neuronowych. Tak złożone układy wymagają zaawansowanych środowisk programistycznych w celu wykorzystania wszystkich dostępnych funkcji.

Celem tego projektu jest przebadanie możliwości architektury ACAP oraz pakietu oprogramowania do inferencji sieci neuronowych


  • Podstawowa znajomość sieci neuronowych
  • Podstawowa znajomość C/C++
  • Podstawowa znajomość technologii FPGA

Investigation of influence of custom data types on neural networks performance

Neural networks are basic tool in artificial intelligence methods, perfectly suitable for inference on FPGAs. Unlike other processing devices, they offer a natural capability of applying custom data types for computations, which in turn, results in higher performance and smaller resource usage.

The aim of this project is to investigate how custom data types affect network learning methods, their architecture and overall performance.


  • Basic knowledge of neural networks
  • Medium knowledge of C++ or Python programming

Sieci neuronowe są podstawowym narzędziem w metodach sztucznej inteligencji, które idealnie nadają się do inferencji na układach FPGA. W przeciwieństwie do innych układów obliczeniowych, oferują naturalną możliwość użycia niestandardowych typów danych, co przekłada się na wyższą wydajność oraz zmniejszone zużycie zasobów.

Celem tego projektu jest przebadanie jak niestandardowe typy danych wpływają na proces uczenia się sieci neuronowych, ich architekturę oraz ogólną wydajność.


  • Podstawowa znajomość sieci neuronowych
  • Średnia znajomość C++ lub Python