JPET Controller power up!

After several ups and downs we have successfully evaluated all the key elements of the JPET Controller and the hardware is ready to use!

In just short time several test projects have been run, including mainly:

  • IBERT (Integrated Bit Error RatioTester) on all the 16x optical links
  • ZYNQ Processing Systems with DDR3 and UART-USB
  • Gigabit Ethernet Module on all the 16x optical links

Now everything is ready to start implementing tomographic data processing!

For more details about the system, please check out this link:

http://www.doit.fais.uj.edu.pl/fpga-jpet-data-analysis

 

Leave a Reply

Fill in your details below or click an icon to log in:

WordPress.com Logo

You are commenting using your WordPress.com account. Log Out /  Change )

Google+ photo

You are commenting using your Google+ account. Log Out /  Change )

Twitter picture

You are commenting using your Twitter account. Log Out /  Change )

Facebook photo

You are commenting using your Facebook account. Log Out /  Change )

Connecting to %s