Conjugate Gradient as benchmark for FPGAs in HPC

During the International Conference on Lattice Field Theory in East Lansing, MI, USA we presented a poster describing our hardware based accelerator for the Dirac matrix inverter. For the first time FPGA devices were shown to be useful in the HPC context discussed at this conference. Several groups expressed their interest in collaboration including the groups from: Michigan State University, Massachusetts Institute of Technology, Brookhaven National Laboratory and China Normal University.

Presented results together with an overview of further development will soon be published. In the meantime you can check out the poster in the results section.

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