All posts by grzegorzkorcyl

New Paper – investigating the dirac operator evaluation on FPGAs

We are pleased to announce that our paper “Investigating the Dirac operator evaluation on FPGAs”, where we describe our research on running accelerated computations on hardware has been published in Supercomputing Frontiers and Innovations vol. 6 no. 2 2019.

Feel free to check it out any time under this [link].

You can find there a description of our kernel performance, evaluated on Xilinx Alveo U250 platforms and developed with SDAccel software package.

Soon we will present a detailed study of various algorithm architectures in order to achieve highest performance and profit from embedded HBM in Alveo U280.

Supercomputing Frontiers Europe 2019

Our recent research results of implementation of Conjugate Gradient as benchmark for HPC solutions was presented during Supercomputing Frontiers Europe 2019 conference in Warsaw 11 – 13 March.

For more details about the conference click [here]

Click [here] to access the presentation.

The talk covers:

  • Implementation of Conjugate Gradient computing kernel with Vivado HLS for Xilinx Alveo U250 platform
  • System design and performance results with the external DDR memory
  • System design and performance results with the embedded memory block

PANDA Straws and DAQ system under beam

February was a month of very intensive work to prepare our straw detector and Data Acquisition System for tests with proton beam from COSY accelerator at Juelich Forschungszentrum in Germany.

Together with 5 other groups we had granted one week of beamtime to evaluate the detectors, electronics and software.

It was the first time we evaluated operation of the entire, small scale detector system for PANDA experiment. Three detector subsystems: Forward Tracker, Electromagnetic Calorimeter and Time-of-Flight, each with their own readout system, were synchronized with SODANet system and generated data was processed by a set of 3 Compute Node modules for burst building and preliminary preprocessing.

It was also the possibility to test the data preprocessing system based on Xilinx ZCU102 platform. The board receives data streams from the digitizing boards and recovers track candidates, rejecting empty events.

Seminar – Using FPGA devices for Lattice QCD

You are welcome to join the seminar by dr. Piotr Korcyl on Tuesday 15th January 2019 at 12:15 in room D-2-02 at the Faculty of Physics, Astronomy and Applied Computer Science of Jagiellonian University.

The talk will cover:

  • implementation of Conjugate Gradient algorithm on Xilinx Zynq MPSoC
  • design methodologies to accelerate computations on FPGA platforms using High Level Synthesis
  • memory management and data transport infrastructure
  • prospects to design an FPGA High Performance Computing platform.

Stereo-camera available

ZED Stereo camera from Stereolabs is available for research projects. It can be easily combined with ZCU104 and ZCU102 platforms which are powered by Zynq MPSoCs. The first one even has an example projects with step-by-step instructions for running a demo project.

The camera is used for depth perpection and motion tracking. Check out the video below:

We plan to evaluate this camera in our PET projects for tracking the patient under scan movement and real-time data corrections based on acquired values.

WEB Frontend builder for Slow Control – Taken

The project is about designing and implementing a configurable frontend interface for Slow Control System for DJPET

Slow Control System allows to control and monitor parameters of the electronics included in the data acquisition system of the DJPET scanner.

The user interface should give a possibility to display values under various forms (e.g.: graphs, raw values etc.) refreshed at time intervals as well as collect input from the user. As the is dynamically developed, the GUI should be easily adjustable by inserting or removing new fields.

Projekt polega na zaprojektowaniu i zaimplementowaniu interfejsu graficznego dla systemu kontrolno/sterującego dla skanera DJPET

System kontrolno/sterujący pozwala na ustawianie i monitorowanie parametrów elektroniki wchodzącej w skład systemu akwizycji danych.

Interfejs użytkownika powinien dawać możliwość prezentowania odczytywanych wartości w różnych formach (grafy, surowe wartości, itp.) odświeżanych w zadanej częstotliwości oraz pozwalać użytkownikowi ustawiać parametry odczytu. Ponieważ system jest dynamicznie rozwijany, GUI powinno mieć możliwość łatwego dodawania  i usuwania nowych pól.