All posts by grzegorzkorcyl

Conjugate Gradient as benchmark for FPGAs in HPC

During the International Conference on Lattice Field Theory in East Lansing, MI, USA we presented a poster describing our hardware based accelerator for the Dirac matrix inverter. For the first time FPGA devices were shown to be useful in the HPC context discussed at this conference. Several groups expressed their interest in collaboration including the groups from: Michigan State University, Massachusetts Institute of Technology, Brookhaven National Laboratory and China Normal University.

Presented results together with an overview of further development will soon be published. In the meantime you can check out the poster in the results section.

D-JPET Readout – Synchronized Aurora Links

Another step towards working system for D-JPET scanner. We have 48 front-end boards that digitize the signals and measure time, readout by 4 concentrator boards. But how synchronize them using a single fiber connection that we have for data transport and control/monitoring?

We have based our data transport infrastructure on default AXI components and Aurora links. One can share a single link between AXI Stream and Memory Mapped applications, which is perfect for our project. This allows to develop a system incredibly fast, basically using block design in Vivado.

But, using the block design, you often get what they give you. So the automatically generated Aurora links have fixed clocking scheme, with no ways to change it using the wizards. One can still take the generated sources and create a custom IP. Then it is easy to change the clocking scheme and synchronize to the clock recovered from the input data stream. And when you realize that there are few bits available in the AXI Stream data bus, you can use them to transport additional information, like synchronization pulses.

III FPGA Symposium – Poster Session Prize!

In order to make things more interesting, Aldec has offered to found a prize for the best poster/demonstration!

Aldec,_Inc._Company_Logo,_Crescent_style.svg

We encourage you to take part in the session – prepare a poster or a demostration of your reasearch or project and compete to win the TySOM-1 board.

All Symposium participants will receive voting forms to fill out throughout the session. At the end we will count the points and the board will go to the winner.

Do not hesitate! Register to the event using the form or use the contact form to register your poster.

HW-based Conjugate Gradient on Conference

Our innovative solution for accelerating the Conjugate Gradient algorithm in Lattice Quantum Chromodynamics has been accepted for a poster presentation during the 36th Annual International Symposium on Lattice Field Theory in East Lansing in USA.

We have developed an accelerator capable of performing double precision computations with peak performance at the level of 750 GFLOPS, entirely implemented in Programmable Logic. It is a unique project of this type and sets an entry point for the development of a distributed and scalable High-Performance Computing platform.

III FPGA Symposium – Training details

Together with KAMAMI we have fixed the details about the training session during III Symposium.

Please check out the updated training page for a complete program of both courses, organization details and registration forms.

Please note that registration for training through Symposium form IS NOT SUFFICIENT. You have to register additionally by clicking on selected training banner.

J-PET on Total Body PET conference

Our J-PET scanner has been one of three main projects for whole-body PET imaging during Total Body PET – From Mice to Men conference.

The contribution of our FPGA-FAIS group was in a form of a poster that highlights main ideas for innovative tomographic data processing. As no other system is doing high-level analysis of this sort on the level of FPGAs we caught a lot of interest.

You can check out the poster under this link.