February was a month of very intensive work to prepare our straw detector and Data Acquisition System for tests with proton beam from COSY accelerator at Juelich Forschungszentrum in Germany.
Together with 5 other groups we had granted one week of beamtime to evaluate the detectors, electronics and software.
It was the first time we evaluated operation of the entire, small scale detector system for PANDA experiment. Three detector subsystems: Forward Tracker, Electromagnetic Calorimeter and Time-of-Flight, each with their own readout system, were synchronized with SODANet system and generated data was processed by a set of 3 Compute Node modules for burst building and preliminary preprocessing.
It was also the possibility to test the data preprocessing system based on Xilinx ZCU102 platform. The board receives data streams from the digitizing boards and recovers track candidates, rejecting empty events.
You are welcome to join the seminar by dr. Piotr Korcyl on Tuesday 15th January 2019 at 12:15 in room D-2-02 at the Faculty of Physics, Astronomy and Applied Computer Science of Jagiellonian University.
The talk will cover:
implementation of Conjugate Gradient algorithm on Xilinx Zynq MPSoC
design methodologies to accelerate computations on FPGA platforms using High Level Synthesis
memory management and data transport infrastructure
prospects to design an FPGA High Performance Computing platform.
ZED Stereo camera from Stereolabs is available for research projects. It can be easily combined with ZCU104 and ZCU102 platforms which are powered by Zynq MPSoCs. The first one even has an example projects with step-by-step instructions for running a demo project.
The camera is used for depth perpection and motion tracking. Check out the video below:
We plan to evaluate this camera in our PET projects for tracking the patient under scan movement and real-time data corrections based on acquired values.
The project is about designing and implementing a configurable frontend interface for Slow Control System for DJPET
Slow Control System allows to control and monitor parameters of the electronics included in the data acquisition system of the DJPET scanner.
The user interface should give a possibility to display values under various forms (e.g.: graphs, raw values etc.) refreshed at time intervals as well as collect input from the user. As the is dynamically developed, the GUI should be easily adjustable by inserting or removing new fields.
Projekt polega na zaprojektowaniu i zaimplementowaniu interfejsu graficznego dla systemu kontrolno/sterującego dla skanera DJPET
System kontrolno/sterujący pozwala na ustawianie i monitorowanie parametrów elektroniki wchodzącej w skład systemu akwizycji danych.
Interfejs użytkownika powinien dawać możliwość prezentowania odczytywanych wartości w różnych formach (grafy, surowe wartości, itp.) odświeżanych w zadanej częstotliwości oraz pozwalać użytkownikowi ustawiać parametry odczytu. Ponieważ system jest dynamicznie rozwijany, GUI powinno mieć możliwość łatwego dodawania i usuwania nowych pól.
September has started – it means that the Symposium is approaching. Have a look at couple updates:
we will keep the registration opened for two more weeks!
Do not hesitate to register to the event using the form.
prizes for the best poster/demonstration
Thanks to our commercial partners Kamami and Aldec the stakes are rising! Prepare your poster or demonstartion to win some nice hardware. Have a look here to find out what you can win and a poster template if you need one.
Check plenary and poster sessions pages to find out our preliminary schedule and topics that will be covered
Last week we finished FPGA Summer Camp 2018 with great results.
Thank you all for cooperation! It was a full month filled with research and hard-work that brought a lot of fun to everyone. Below you can find some slides from participants that sum up our work a bit:
During the International Conference on Lattice Field Theory in East Lansing, MI, USA we presented a poster describing our hardware based accelerator for the Dirac matrix inverter. For the first time FPGA devices were shown to be useful in the HPC context discussed at this conference. Several groups expressed their interest in collaboration including the groups from: Michigan State University, Massachusetts Institute of Technology, Brookhaven National Laboratory and China Normal University.
Presented results together with an overview of further development will soon be published. In the meantime you can check out the poster in the results section.