Our system for data acquisition from tracking detectors, based on TRBv3 platform has been presented at IEEE Real Time Conference 2016 in Padova.
It is worth to mention that the TRBv3 platform itself found its place on several other contributions at that conference!
More hardware to explore! We have been just granted DE1-SoC and DE5 development kits from ALTERA by their university program.
- DE1-SoC is a Cyclone V based paltform:
- DE5 is an advanced Stratix V platform:
Great HDL development IDE SIGASI has just provided a couple of licenses for our group. Their advanced, Eclipse-based software is a significant support in the logic development mostly thanks to real-time syntax check and code decomposition that provides auto-completition, something so much appreciated when writing in VHDL 😉
Great news! We have received additional founding from the faculty in the program DSC2016.
It is a clear sign that our effort in propagating FPGA technology as an important branch in Computer Science and Experimental Physics related projects has been noticed and appreciated.
Here’s what we’ll buy in the near future:
- Advanced Zynq-based development kit ZC706
- Two basic, Artix-based development kits Arty
Thanks to ALTERA for supporting us by donating a set of licenses for their Quartus design tools. We are awaiting development boards and hardware as well.
On Monday 2nd of May 2016 we have finished a successfull, two-week beamtime in Forschungszentrum Juelich GmbH for our prototype of Forward Tracker constructed for PANDA (FAIR, Germany).
Great amount of work was needed in order to condition the detector and also for the design and evaluation of its FPGA-based readout system.
The use of TRBv3 hardware together with the software environment for data processing, resulted in very smooth data collection and achievement of low-noise, high-resolution results.
After several ups and downs we have successfully evaluated all the key elements of the JPET Controller and the hardware is ready to use!
In just short time several test projects have been run, including mainly:
- IBERT (Integrated Bit Error RatioTester) on all the 16x optical links
- ZYNQ Processing Systems with DDR3 and UART-USB
- Gigabit Ethernet Module on all the 16x optical links
Now everything is ready to start implementing tomographic data processing!
For more details about the system, please check out this link: