Thanks to ALTERA for supporting us by donating a set of licenses for their Quartus design tools. We are awaiting development boards and hardware as well.
On Monday 2nd of May 2016 we have finished a successfull, two-week beamtime in Forschungszentrum Juelich GmbH for our prototype of Forward Tracker constructed for PANDA (FAIR, Germany).
Great amount of work was needed in order to condition the detector and also for the design and evaluation of its FPGA-based readout system.
The use of TRBv3 hardware together with the software environment for data processing, resulted in very smooth data collection and achievement of low-noise, high-resolution results.
After several ups and downs we have successfully evaluated all the key elements of the JPET Controller and the hardware is ready to use!
In just short time several test projects have been run, including mainly:
- IBERT (Integrated Bit Error RatioTester) on all the 16x optical links
- ZYNQ Processing Systems with DDR3 and UART-USB
- Gigabit Ethernet Module on all the 16x optical links
Now everything is ready to start implementing tomographic data processing!
For more details about the system, please check out this link:
Both journals are now available for you to check out in selected seminar rooms. Latest releases will keep coming in.
According to the publisher:
Xcell Journal offers a wealth of practical engineering knowledge and in-depth coverage of the latest applications and technologies.
Xcell Software Journal offers a wealth of practical knowledge and in-depth coverage of the latest applications and methods for software and system design.
Take a look and enjoy!
A large FPGA-based Data Acquisition Systems for JPET tomograph prototype is up and running!
The system consists of 9x TRBv3 modules running in 1x Master – 8x Slaves mode, collecting data from 384 photomultipliers, delivering signals to 1536 high-resolution TDC channels.
Generated data stream is forwarded into 3x 1Gb network interfaces of a server class rack computer. We are awaiting for the founds dedicated to network upgrade to 10Gb solutions.
Great hardware and software solutions allow to display data quality histograms constructed in the real time as well as storing data for further offline processing.
For more details about the readout system, please check out the link:
I’m glad to announce that we have managed to acquire a generous donation for Xilinx Inc.
The entire package contains:
- 2x ZedBoard development kit
- 25x Vivado HLx: System Edition license
Looking forward further fruitful cooperation!
With the new semester we start weekly meetings dedicated to FPGA technology. It’s a great place to discuss, consult and learn about various aspects of logic development.
The meetings take place in G-1-08 each Tuesday at 16:00.
Everybody is welcome to come!