high performance computing – fast interconnect

High Performance Computing systems are composed of many interconnected nodes, where each one of them computes its individual part of the algorithm. Considering the performance of the nodes, memory access or data delivery becomes a bottleneck not only in terms of bytes per second but also in terms of latency.

The aim of this project is to review recent networking standards and their implementation on FPGA devices for High Performance Computing systems.

Requirements:

  • Basic knowledge of computer networking
  • Basic knowledge of HDL programming

Systemy typu High Performance Computing są złożone z wielu, połączonych pomiędzy sobą węzłów, z których każdy oblicza pewną część algorytmu. Uwzględniając wydajność węzłów, wąskim gardłem staje się dostęp do pamięci oraz dostarczanie danych, nie tylko w kategorii bajtów na sekundę ale również opóźnienia.

Celem tego projektu jest przegląd nowoczesnych standardów komunikacyjnych oraz ich implementacja na układach FPGA.

Wymagania:

  • Podstawowa znajomość sieci komputerowych
  • Podstawowa znajomość programowania HDL

high performance computing – computing kernel

Just like GPUs 20 years ago, now FPGA devices enter High Performance Computing systems for accelerating computations. Modern development techniques allow to design such systems in C/C++ or OpenCL. By effective usage of FPGA major advantages such as pipelined processing and natural parallelism one can gain superior performance over other computing devices.

The aim of this project is to implement a common stencil code and investigate its performance on FPGA platforms.

Requirements:

  • Basic knowledge of C/C++ programming

Tak jak układy GPU 20 lat temu, tak teraz układy FPGA zaczynają być używane w systemach typu High Performance Computing w celu akceleracji obliczeń. Nowoczesne metody rozwoju oprogramowania pozwalają implementować takie systemy przy użyciu C/C++ lub OpenCL. Poprzez efektywne wykorzystanie głównych zalet układów FPGA takich jak strumieniowe przetwarzanie danych oraz naturalne zrównoleglanie obliczeń, można osiągnąć wyższą wydajność niż inne układu obliczeniowe.

Celem tego projektu jest implementacja algorytmu szablonowego oraz analiza jest wydajność na platformach z układami FPGA.

Wymagania:

  • Podstawowa znajomość C/C++

New Paper – investigating the dirac operator evaluation on FPGAs

We are pleased to announce that our paper “Investigating the Dirac operator evaluation on FPGAs”, where we describe our research on running accelerated computations on hardware has been published in Supercomputing Frontiers and Innovations vol. 6 no. 2 2019.

Feel free to check it out any time under this [link].

You can find there a description of our kernel performance, evaluated on Xilinx Alveo U250 platforms and developed with SDAccel software package.

Soon we will present a detailed study of various algorithm architectures in order to achieve highest performance and profit from embedded HBM in Alveo U280.

Supercomputing Frontiers Europe 2019

Our recent research results of implementation of Conjugate Gradient as benchmark for HPC solutions was presented during Supercomputing Frontiers Europe 2019 conference in Warsaw 11 – 13 March.

For more details about the conference click [here]

Click [here] to access the presentation.

The talk covers:

  • Implementation of Conjugate Gradient computing kernel with Vivado HLS for Xilinx Alveo U250 platform
  • System design and performance results with the external DDR memory
  • System design and performance results with the embedded memory block

PANDA Straws and DAQ system under beam

February was a month of very intensive work to prepare our straw detector and Data Acquisition System for tests with proton beam from COSY accelerator at Juelich Forschungszentrum in Germany.

Together with 5 other groups we had granted one week of beamtime to evaluate the detectors, electronics and software.

It was the first time we evaluated operation of the entire, small scale detector system for PANDA experiment. Three detector subsystems: Forward Tracker, Electromagnetic Calorimeter and Time-of-Flight, each with their own readout system, were synchronized with SODANet system and generated data was processed by a set of 3 Compute Node modules for burst building and preliminary preprocessing.

It was also the possibility to test the data preprocessing system based on Xilinx ZCU102 platform. The board receives data streams from the digitizing boards and recovers track candidates, rejecting empty events.

Seminar – Using FPGA devices for Lattice QCD

You are welcome to join the seminar by dr. Piotr Korcyl on Tuesday 15th January 2019 at 12:15 in room D-2-02 at the Faculty of Physics, Astronomy and Applied Computer Science of Jagiellonian University.

The talk will cover:

  • implementation of Conjugate Gradient algorithm on Xilinx Zynq MPSoC
  • design methodologies to accelerate computations on FPGA platforms using High Level Synthesis
  • memory management and data transport infrastructure
  • prospects to design an FPGA High Performance Computing platform.

Stereo-camera available

ZED Stereo camera from Stereolabs is available for research projects. It can be easily combined with ZCU104 and ZCU102 platforms which are powered by Zynq MPSoCs. The first one even has an example projects with step-by-step instructions for running a demo project.

The camera is used for depth perpection and motion tracking. Check out the video below:

We plan to evaluate this camera in our PET projects for tracking the patient under scan movement and real-time data corrections based on acquired values.

WEB Frontend builder for Slow Control

The project is about designing and implementing a configurable frontend interface for Slow Control System for DJPET

Slow Control System allows to control and monitor parameters of the electronics included in the data acquisition system of the DJPET scanner.

The user interface should give a possibility to display values under various forms (e.g.: graphs, raw values etc.) refreshed at time intervals as well as collect input from the user. As the is dynamically developed, the GUI should be easily adjustable by inserting or removing new fields.

Projekt polega na zaprojektowaniu i zaimplementowaniu interfejsu graficznego dla systemu kontrolno/sterującego dla skanera DJPET

System kontrolno/sterujący pozwala na ustawianie i monitorowanie parametrów elektroniki wchodzącej w skład systemu akwizycji danych.

Interfejs użytkownika powinien dawać możliwość prezentowania odczytywanych wartości w różnych formach (grafy, surowe wartości, itp.) odświeżanych w zadanej częstotliwości oraz pozwalać użytkownikowi ustawiać parametry odczytu. Ponieważ system jest dynamicznie rozwijany, GUI powinno mieć możliwość łatwego dodawania  i usuwania nowych pól.

Hardware shelf update

Thanks to the department funding we have updated the hardware available for various projects. Do you have an idea for a project? Check out the list of boards and equipment below:

  • ZCU102 – Zynq MPSoC EG: advanced platform for all sorts of projects: networking, computing, video processing and much more

zcu102

  • ZCU104 – Zynq MPSoC EV: great for advanced video processing and HPC applications

zcu104

  • ZC706 – Zynq 45: Versatile platform for evaluation of System-on-Chip architectures

zc706

  • ZYBO Z7 – Zynq 20: powerful and compact platform for various entry projects

zybo-z7-4

  • KC705 – Kintex 325: versatile platform for evaluation of Kintex devices

kc705

  • ZedBoard Zynq 20: universal Zynq platform for entry projects

zedboard

  • ZED: stereo camera, compatible with ZCU104 platforms

zed_stereo

  • PCAM: video camera for Zybo platforms

Pcam_5C

  • MTDS PMod: LCD screen with touch support

PmodMTDS

  • NAV PMod: 9-axis IMU sensor

Pmod_NAV

  • And much more! Feel free to contact us in case you need some support