Thanks to the department funding we have updated the hardware available for various projects. Do you have an idea for a project? Check out the list of boards and equipment below:
- ZCU102 – Zynq MPSoC EG: advanced platform for all sorts of projects: networking, computing, video processing and much more
- ZCU104 – Zynq MPSoC EV: great for advanced video processing and HPC applications
- ZC706 – Zynq 45: Versatile platform for evaluation of System-on-Chip architectures
- ZYBO Z7 – Zynq 20: powerful and compact platform for various entry projects
- KC705 – Kintex 325: versatile platform for evaluation of Kintex devices
- ZedBoard Zynq 20: universal Zynq platform for entry projects
- ZED: stereo camera, compatible with ZCU104 platforms
- PCAM: video camera for Zybo platforms
- MTDS PMod: LCD screen with touch support
- NAV PMod: 9-axis IMU sensor
- And much more! Feel free to contact us in case you need some support
The project is about designing and implementing a Slow Control System for DJPET
Slow Control System allows to control and monitor parameters of the electronics included in the data acquisition system of the DJPET scanner.
The system is based on the AXI components, which are mapped to the master device memory. In our case the master is the Linux on ARM embedded in the Zynq MPSoC. The project consists of developing software that will be able to read and write to any AXI component in the system as well as perform fundamental tasks like remote rebooting, flashing etc.
Projekt polega na zaprojektowaniu i zaimplementowaniu systemu kontrolno/sterującego dla skanera DJPET
System kontrolno/sterujący pozwala na ustawianie i monitorowanie parametrów elektroniki wchodzącej w skład systemu akwizycji danych.
System akwizycji bazuje na komponentach AXI, które są mapowane w pamięci głównego układu. W naszym przypadku, tym głównym układem jest system Linux działający na procesorze ARM wbudowanym w układ Zynq MPSoC. Projekt polega na rozwinięciu oprogramowania pozwalającego czytac i pisać po rejestrach każdego komponentu AXI oraz przeprowadzać podstawowe operacje takie jak restartowanie układów czy programowanie pamięci flash.
We are happy to announce that our research on hardware acceleration of Conjugate Gradient algorithm has been written down in a form of a publication.
Feel free to check it out any time under this [link].
It has been also submitted to a major computer science journal. We are looking forward to receive reviewers opinions in the near future.
Thanks to all participants we had a great conference last week! Check out the short summary with handful of interesting stats and links.
on training day, a total of 40 participants exercised Intel or Xilinx FPGAs
during the symposium day we had 9 talks and 18 demonstrations
- check the plenary and poster sessions pages for full lists, abstracts and slides
over 75 people showed up and up to 30 watched the online stream
you can watch the recorded plenary session on youtube at any time using this [link]
Poster/demonstration session results:
1st place: mgr inż. Paweł Jurgielewicz (AGH)
- Realistic three-dimensional graphics accelerator using Vivado HLS for FPGA devices
2nd place: Patryk Frączek (AGH)
- Hardware-software vision system for the detection of safe landing sites for UAVs
- Michał Znaleźniak and Szymon Pulut (UJ)
- Karol Radwan (AGH)
- Hardware-software implementation of a SFM module for navigation of UAV
- Mgr inż. Piotr Rzeszut (AGH)
- Oscilloscope based on small-size FPGA with VGA display
Congratulations to all participants!
Thanks to KAMAMI and ALDEC for funding the prizes for contestants.
All those who cannot be today at Jagiellonian University on symposium are kindly invited to watch live stream on YouTube.
September has started – it means that the Symposium is approaching. Have a look at couple updates:
- we will keep the registration opened for two more weeks!
Do not hesitate to register to the event using the form.
- prizes for the best poster/demonstration
Thanks to our commercial partners Kamami and Aldec the stakes are rising! Prepare your poster or demonstartion to win some nice hardware. Have a look here to find out what you can win and a poster template if you need one.
Check plenary and poster sessions pages to find out our preliminary schedule and topics that will be covered
Last week we finished FPGA Summer Camp 2018 with great results.
Thank you all for cooperation! It was a full month filled with research and hard-work that brought a lot of fun to everyone. Below you can find some slides from participants that sum up our work a bit:
All projects were developed mostly using High Level Synthesis and form nice base projects, which can now be extended.
If you are interested in any of those topics, feel free to register to FPGA Symposium 2018 where most of them will be presented during the poster/demonstration session!
The summer comes to an end, but in case you would be interested in developing your own project, contact us at any time.