Slow Control System for DJPET DAQ – TAKEN

The project is about designing and implementing a Slow Control System for DJPET

Slow Control System allows to control and monitor parameters of the electronics included in the data acquisition system of the DJPET scanner.

The system is based on the AXI components, which are mapped to the master device memory. In our case the master is the Linux on ARM embedded in the Zynq MPSoC. The project consists of developing software that will be able to read and write to any AXI component in the system as well as perform fundamental tasks like remote rebooting, flashing etc.

Projekt polega na zaprojektowaniu i zaimplementowaniu systemu kontrolno/sterującego dla skanera DJPET

System kontrolno/sterujący pozwala na ustawianie i monitorowanie parametrów elektroniki wchodzącej w skład systemu akwizycji danych.

System akwizycji bazuje na komponentach AXI, które są mapowane w pamięci głównego układu. W naszym przypadku, tym głównym układem jest system Linux działający na procesorze ARM wbudowanym w układ Zynq MPSoC. Projekt polega na rozwinięciu oprogramowania pozwalającego czytac i pisać po rejestrach każdego komponentu AXI oraz przeprowadzać podstawowe operacje takie jak restartowanie układów czy programowanie pamięci flash.

III FPGA Symposium – Summary

Thanks to all participants we had a great conference last week! Check out the short summary with handful of interesting stats and links.

  • on training day, a total of 40 participants exercised Intel or Xilinx FPGAs

  • during the symposium day we had 9 talks and 18 demonstrations

    • check the plenary and poster sessions pages for full lists, abstracts and slides
  • over 75 people showed up and up to 30 watched the online stream

  • you can watch the recorded plenary session on youtube at any time using this [link]

  • Poster/demonstration session results:

    • 1st   place: mgr inż. Paweł Jurgielewicz (AGH)

      • Realistic three-dimensional graphics accelerator using Vivado HLS for FPGA devices
    • 2nd place: Patryk Frączek (AGH)

      • Hardware-software vision system for the detection of safe landing sites for UAVs
    • 3rd place:

      • Michał Znaleźniak and Szymon Pulut (UJ)
        • tANS compression system
      • Karol Radwan (AGH)
        • Hardware-software implementation of a SFM module for navigation of UAV
      • Mgr inż. Piotr Rzeszut (AGH)
        • Oscilloscope based on small-size FPGA with VGA display

Congratulations to all participants!

Thanks to KAMAMI and ALDEC for funding the prizes for contestants.

III FPGA Symposium – Update

September has started – it means that the Symposium is approaching. Have a look at couple updates:

  • we will keep the registration opened for two more weeks!

Do not hesitate to register to the event using the form.

  • prizes for the best poster/demonstration

Thanks to our commercial partners Kamami and Aldec the stakes are rising! Prepare your poster or demonstartion to win some nice hardware. Have a look here to find out what you can win and a poster template if you need one.

  • preliminary schedules

Check plenary and poster sessions pages to find out our preliminary schedule and topics that will be covered

 

End of FPGA Summer Camp 2018

Last week we finished FPGA Summer Camp 2018 with great results.

Thank you all for cooperation! It was a full month filled with research and hard-work that brought a lot of fun to everyone. Below you can find some slides from participants that sum up our work a bit:

All projects were developed mostly using High Level Synthesis and form nice base projects, which can now be extended.

If you are interested in any of those topics, feel free to register to FPGA Symposium 2018 where most of them will be presented during the poster/demonstration session!

The summer comes to an end, but in case you would be interested in developing your own project, contact us at any time.

We are in half-way point of FPGA Summer Camp 2018

We have just finished second week of the FPGA Summer Camp 2018.

Today attendees presented their recent work and research in given topics. All projects are currently being developed in High Level Synthesis and present modern trends in applications where FPGAs are considered. Below you can find a list of projects:

  • Development of encoding engine for tANS data compression algorithm
  • Research on High Performance Computing – evaluation of LINPACK benchmarks on FPGAs
  • Video processing – drawing 3D objects, dynamically controlled by an IMU sensor on HDMI stream
  • Machine learning – neural network trained on MNIST data set inference
  • Analysis of hashing algorithms for cryptocurrency mining

Stay tuned for more details and results!