We are happy to announce that our research on hardware acceleration of Conjugate Gradient algorithm has been written down in a form of a publication.
Feel free to check it out any time under this [link].
It has been also submitted to a major computer science journal. We are looking forward to receive reviewers opinions in the near future.
Thanks to all participants we had a great conference last week! Check out the short summary with handful of interesting stats and links.
on training day, a total of 40 participants exercised Intel or Xilinx FPGAs
during the symposium day we had 9 talks and 18 demonstrations
- check the plenary and poster sessions pages for full lists, abstracts and slides
over 75 people showed up and up to 30 watched the online stream
you can watch the recorded plenary session on youtube at any time using this [link]
Poster/demonstration session results:
1st place: mgr inż. Paweł Jurgielewicz (AGH)
- Realistic three-dimensional graphics accelerator using Vivado HLS for FPGA devices
2nd place: Patryk Frączek (AGH)
- Hardware-software vision system for the detection of safe landing sites for UAVs
- Michał Znaleźniak and Szymon Pulut (UJ)
- Karol Radwan (AGH)
- Hardware-software implementation of a SFM module for navigation of UAV
- Mgr inż. Piotr Rzeszut (AGH)
- Oscilloscope based on small-size FPGA with VGA display
Congratulations to all participants!
Thanks to KAMAMI and ALDEC for funding the prizes for contestants.
All those who cannot be today at Jagiellonian University on symposium are kindly invited to watch live stream on YouTube.
September has started – it means that the Symposium is approaching. Have a look at couple updates:
- we will keep the registration opened for two more weeks!
Do not hesitate to register to the event using the form.
- prizes for the best poster/demonstration
Thanks to our commercial partners Kamami and Aldec the stakes are rising! Prepare your poster or demonstartion to win some nice hardware. Have a look here to find out what you can win and a poster template if you need one.
Check plenary and poster sessions pages to find out our preliminary schedule and topics that will be covered
Last week we finished FPGA Summer Camp 2018 with great results.
Thank you all for cooperation! It was a full month filled with research and hard-work that brought a lot of fun to everyone. Below you can find some slides from participants that sum up our work a bit:
All projects were developed mostly using High Level Synthesis and form nice base projects, which can now be extended.
If you are interested in any of those topics, feel free to register to FPGA Symposium 2018 where most of them will be presented during the poster/demonstration session!
The summer comes to an end, but in case you would be interested in developing your own project, contact us at any time.
We have just finished second week of the FPGA Summer Camp 2018.
Today attendees presented their recent work and research in given topics. All projects are currently being developed in High Level Synthesis and present modern trends in applications where FPGAs are considered. Below you can find a list of projects:
- Development of encoding engine for tANS data compression algorithm
- Research on High Performance Computing – evaluation of LINPACK benchmarks on FPGAs
- Video processing – drawing 3D objects, dynamically controlled by an IMU sensor on HDMI stream
- Machine learning – neural network trained on MNIST data set inference
- Analysis of hashing algorithms for cryptocurrency mining
Stay tuned for more details and results!
During the International Conference on Lattice Field Theory in East Lansing, MI, USA we presented a poster describing our hardware based accelerator for the Dirac matrix inverter. For the first time FPGA devices were shown to be useful in the HPC context discussed at this conference. Several groups expressed their interest in collaboration including the groups from: Michigan State University, Massachusetts Institute of Technology, Brookhaven National Laboratory and China Normal University.
Presented results together with an overview of further development will soon be published. In the meantime you can check out the poster in the results section.
Another step towards working system for D-JPET scanner. We have 48 front-end boards that digitize the signals and measure time, readout by 4 concentrator boards. But how synchronize them using a single fiber connection that we have for data transport and control/monitoring?
We have based our data transport infrastructure on default AXI components and Aurora links. One can share a single link between AXI Stream and Memory Mapped applications, which is perfect for our project. This allows to develop a system incredibly fast, basically using block design in Vivado.
But, using the block design, you often get what they give you. So the automatically generated Aurora links have fixed clocking scheme, with no ways to change it using the wizards. One can still take the generated sources and create a custom IP. Then it is easy to change the clocking scheme and synchronize to the clock recovered from the input data stream. And when you realize that there are few bits available in the AXI Stream data bus, you can use them to transport additional information, like synchronization pulses.
In order to make things more interesting, Aldec has offered to found a prize for the best poster/demonstration!
We encourage you to take part in the session – prepare a poster or a demostration of your reasearch or project and compete to win the TySOM-1 board.
All Symposium participants will receive voting forms to fill out throughout the session. At the end we will count the points and the board will go to the winner.
Do not hesitate! Register to the event using the form or use the contact form to register your poster.
Our innovative solution for accelerating the Conjugate Gradient algorithm in Lattice Quantum Chromodynamics has been accepted for a poster presentation during the 36th Annual International Symposium on Lattice Field Theory in East Lansing in USA.
We have developed an accelerator capable of performing double precision computations with peak performance at the level of 750 GFLOPS, entirely implemented in Programmable Logic. It is a unique project of this type and sets an entry point for the development of a distributed and scalable High-Performance Computing platform.