Implementation of image reconstruction from tomographic data has been presented for the first time to external experts in tomography at two conferences. First one was XL IEEE-SPIE Joint Symposium Wilga 2017 and the second one was 2nd Jagiellonian Symposium on Fundamental and Subatomic Physics
The project received much interest from the experts from USA universities and was reviewed as having much potential in development of true innovative solutions, not existing on market so far.
Another step into tomographic image reconstruction in real time has been made!
JPET Controller allows to process data from 8 TRBv3s in several steps leading to image creation:
All those steps, performed 50 000 times per second, processing hundreds MB per second reduce the data volume to hundreds of KB and limit the processing on the CPU only to drawing points. All this on a single Xilinx Zynq.
Next steps are:
Under this [link] you can find a video that shows reconstructed image being drawn in real time as the radioactive source on robotic arm scans the detector.
First images have been produced by JPET Controller board!
The controller processes data streams from 8 TRBs, parses the TDC data and recovers hits on scintillators. The hits are correlated together by scanning with a time window and then mapped into the detector geometry in order to recover LOR coordinates. Finally instead of raw TDC data only two points from LOR are being sent.
After several ups and downs we have successfully evaluated all the key elements of the JPET Controller and the hardware is ready to use!
In just short time several test projects have been run, including mainly:
Now everything is ready to start implementing tomographic data processing!
For more details about the system, please check out this link:
http://www.doit.fais.uj.edu.pl/fpga-jpet-data-analysis
A large FPGA-based Data Acquisition Systems for JPET tomograph prototype is up and running!
The system consists of 9x TRBv3 modules running in 1x Master – 8x Slaves mode, collecting data from 384 photomultipliers, delivering signals to 1536 high-resolution TDC channels.
Generated data stream is forwarded into 3x 1Gb network interfaces of a server class rack computer. We are awaiting for the founds dedicated to network upgrade to 10Gb solutions.
Great hardware and software solutions allow to display data quality histograms constructed in the real time as well as storing data for further offline processing.
For more details about the readout system, please check out the link:
http://www.doit.fais.uj.edu.pl/fpga-trbv3-platform
FPGA FAIS 