We had a great pleasure to participate in Digilent Design Contest 2018 finals. Competition was strong this year. Team from Serbia won first prize with their Deep Neural Network Hardware Accelerator.
On the podium was also one team from Romania and two from Poland.
Additive Synthesizer – Gdansk University of Technology
was granted with Digilent special prize for best usage of Digilent Instruments.
The event lasts for two days. On Saturday all finalists were presenting their work. On Sunday only few teams were invited for showing in details their solutions.
Most of submissions for the contest were diploma thesis or long-term projects conducted by experienced engineers.
Our approach for competition was to learn a lot and explore different approaches to Augmented Reality on SoC devices. In my opinion it is not necessarily important to win, but to compete, cooperate and learn state-of-the-art techniques and methods. We draw conclusions and got valuable feedback from community.
Congratulations to our team developing the Augmented Reality Playground project for the Digilent Design Contest!
The mid term report has been accepted and they are qualified for the finals in Cluj-Napoca in Romania.
We have successfully managed to construct the first ever mini PANDA DAQ system!
Two subsystems: FT straws and EMC are working together, synchronized by SODANet and processed by Burst Building Network constructed out of 3 Compute Node modules.
First cosmics were collected and tracks reconstructed!
Today we have run our first full implementation of LSTM neural network on Xilinx Zynq MPSoC ZCU102 platform!
There are 8 hardware accelerators to help the ARM performing successive stages of the network evaluation.
We have achieved over 20x acceleration comparing to pure-software implementation.
The project has been entirely developed in SDSoC environment.
We have just received an information that our young team has been qualified to Digilent Design Contest!
They will develop a demonstration of a simple Augmented Reality device on Zybo platform.
Enhanced image reconstruction, including 3D and TOF functionalities has been successfully implemented entirely in the FPGA!
In programmable logic, we are finding LOR candidates and reconstruct the annihilation point coordinates. Then, only X, Y, Z values are being sent from the JPET Controller to the server that produces 3D canvas with the scanner visualization.
You can find a video showing it in action under [this] link.