Things are getting serious!
Together with the official annoucement of the J-PET Lab opening [link] we are shifting up a gear: there is plenty of FPGA related development, both in low level RTL and HLS. If you are interested, have a look at diploma projects tab or email directly at firstname.lastname@example.org
[Visualization by email@example.com]
Another step towards working system for D-JPET scanner. We have 48 front-end boards that digitize the signals and measure time, readout by 4 concentrator boards. But how synchronize them using a single fiber connection that we have for data transport and control/monitoring?
We have based our data transport infrastructure on default AXI components and Aurora links. One can share a single link between AXI Stream and Memory Mapped applications, which is perfect for our project. This allows to develop a system incredibly fast, basically using block design in Vivado.
But, using the block design, you often get what they give you. So the automatically generated Aurora links have fixed clocking scheme, with no ways to change it using the wizards. One can still take the generated sources and create a custom IP. Then it is easy to change the clocking scheme and synchronize to the clock recovered from the input data stream. And when you realize that there are few bits available in the AXI Stream data bus, you can use them to transport additional information, like synchronization pulses.
Our processing rack is growing up. Today we have installed Virtex Ultrascale based data concentrators inside the rack and connected to the DAQ server. Integrated processing, real time processing and a screen will give an instant overview of the measurement.
Do not be fooled by the photo, there are wheels under the rack.
I’m glad to announce that we have managed to acquire a generous donation for Xilinx Inc.
The entire package contains:
- 2x ZedBoard development kit
- 25x Vivado HLx: System Edition license
Looking forward further fruitful cooperation!